Work Experience

    1. SynTest Technologies, Inc., 06/2015 – Present
Superior: Dr. Laung-Terng Wang, President & CEO
Position: Intern
Description: Studying Design-for-Test (DFT) related knowledge and automating UltraScan.

I. Studying DFT architectures and test techniques: Studying DFT architectures and test techniques, including Scan Design, Test Compression, Logic Built-In Self-Test (BIST), Boundary-Scan (IEEE Std 1149.1), and Core-Based Testing, particularly, those supported at SynTest.

II. Low-Pin-Count Scan Compression Software (UltraScan) Automation: Automating UltraScan, SynTest low-pin-count scan compression synthesis tool, to further reduce test application time, including enhancing its existing Standard Test Interface Language (STIL) parser to fully comply with the IEEE Std 1450.6. UltraScan uses a time-division multiplexing/demultiplexing technique to shift scan patterns and test responses in and out of scan chains at a higher speed. This work is still on-going and expected to be completed around March 2016.

    2. Cadence Design Systems, Inc., Shanghai, 03/2012 – 06/2014
Superior: Taufik Arifin, Group Director of Product Engineering
Position: Product Engineer (PE)

Description: I worked in the PE team which took care of all stages of the Encounter Digital Implementation (EDI) backend design flow, including Floorplan, Placement, Timing Optimization, Power Optimization, Clock Tree Synthesis, Routing and Engineering Change Order (ECO) . My area of concentration was ECO which included pre-mask ECO and post-mask ECO.

I. Customer Support: Optimized and maintained ECO flow in EDI for better performance, co-worked with Cadence Conformal ECO PE to provide a complete ECO solution from frontend functional ECO to backend physical ECO implementation; Developed customized programs written in PERL or TCL language per customers’ technical requirements; Delivered customers on-site support for urgent issues and provided presentations regarding ECO new features and solutions.

II. R&D Engineer Support: Evaluated and analyzed the feasibility of all EDI ECO enhancement requirements from customers; Developed behavioral models and provided technical specifications for R&D engineers based on the feasibility analysis.

III. Product Validation Engineer Support: Developed test patterns for functional validation of new EDI ECO features; Reviewed and evaluated test specifications provided by PV engineers in order to ensure the test coverage and validity.

    3. Cadence Design Systems, Inc., Shanghai, 06/2011 – 03/2012
Superior: Hong Xu, Sr. PV Manager
Position: Product Validation (PV) Intern

Description: The group I joined was EDI Global Physical Synthesis (GPS) PV team, which worked on Timing/Area/Power/Signal Integrity (SI) optimization. My work concentrated in timing optimization test case review for pre-CTS, post-CTS and post-Route stages.

I. Regression Test & Analysis: Analyzed all failure PV test cases to find and report EDI bugs; Migrated all test cases into Multi-Mode Multi-Corner (MMMC) mode for supporting a new feature which provided customer a flexible solution to select different combinations of modes & corners when timing analysis and optimization.

II. New Feature Testing: Developed test programs and tested multi-CPU supporting performance of the engine for timing optimization.

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