Projects

GRADUATE RESEARCH

 

    1. Low-Power Bus Encoding Scheme for AMBA Based System-on-Chip (SoC) Design, 03/2011 – 11/2011
LAB: System Level Chip Design Center, School of Microelectronics, SJTU
Advisors: Professor Qin Wang and Dr. Jing Xie
Description:

I developed a low-power bus encoding scheme which significantly reduced dynamic power introduced by crosstalk on AMBA Advanced High-performance Bus (AHB) and the AMBA Advanced eXtensible Interface (AXI). Dynamic power caused by crosstalk is measured by the number of coupling transitions, which is defined as the ratio of coupling capacitance over substrate capacitance. My encoding scheme was based on a traditional bus encoding scheme, named Even/Odd Bus Invert (E/O BI). But the E/O BI bus encoding scheme could even increase the number of coupling transitions in some cases. I solved this problem and made further improvement by taking advantage of the special characteristics of AHB and AXI, especially the AHB address bus. For instance, by only encoding a subset of data in a burst operation and utilizing the existing control signals to control the encoder and decoder, extra area cost was saved. The experiment results showed that my encoding scheme reduced up to 51.47% coupling transitions. My paper was published on these findings in the World Congress on Engineering and Technology (CET) in 2011. For more information, please refer to the paper.

Improved EO BI enconder hardware Amba based SoC platform

(left) Improved E/O BI encoder hardware;  (right) The AMBA-based SoC platform

    2. Peripheral Intellectual Property (IP) Core Design (Government Property), 08/2010 – 02/2011
LAB: System Level Chip Design Center, School of Microelectronics, SJTU
Advisors: Professor Qin Wang and Dr. Jing Xie
Description:

I developed a Serial Peripheral Interface (SPI) and a General Purpose Input Output (GPIO) for AMBA-based multi-core SoC design. Both of them were mounted on AMBA Advanced Peripheral Bus (APB). In order to enable their communication with master devices mounted on AMBA AHB bus, I also implemented an APB2AHB bridge.

apb2ahb

State machine for the APB2AHB bridge

    3. FFT-based Chirp Scaling Algorithm (CSA) Implementation (Government Property), 06/2010 – 07/2010
LAB: System Level Chip Design Center, School of Microelectronics, SJTU
Advisor: Professor Qin Wang
Description:

I implemented the FFT-based Chirp Scaling Algorithm (CSA) for Synthetic Aperture Radar (SAR) data processing in a C program. Its purpose was to evaluate a 16-core DSP architecture adopted in an AMBA-based multi-core SoC design. The DSP architecture contained a 4 by 4 Processing Element (PE) array. Each PE had a 2k-byte instruction memory and a 4k-byte data memory. Each row consisted of 4 PEs with a shared 8k-byte cache memory bank. I first implemented the algorithm in a C program. In order to evaluate the parallel computing ability and the memory cost of the DSP architecture, I later partitioned the C program into 4 steps so that 4 PEs in each row in the array could process 4 steps at the same time. Meanwhile, I divided the SAR data into 4 parts. With this arrangement, 4 PEs in each column in the array could process 4 SAR data parts simultaneously. The SAR data transferred between every single PE was stored in a shared cache memory bank to save memory cost.

UNDERGRADUATE RESEARCH

 

    1. A Genetic Algorithm (GA) Based PID Parameters Optimization System, 03/2009 – 09/2009
LAB: Automation and Control Research Center, College of Automation, NJUPT
Advisor: Professor Jie Luo
Description:

I designed a PID (proportion, integral, differential) optimizer for a negative-feedback control system using the MATLAB Genetic Algorithm (GA) Tool. The optimizer was used to search for a set of PID parameters in obtaining an optimal step response, which had smaller overshoot and better rate of convergence compared to traditional methods. I built a PID controller model in MATLAB SIMULINK to imitate the fitness function required by the GA tool. And I developed a closed-loop system allowing real-time communication between the PID optimizer and the PID controller model. For more information, please refer to the research report.

step response new

Step response using GA compared to using traditional methods (GA vs. Ziegler-Niehols, Cohen-Coon and Stability Boundary)

    2. A Bus Transit Trip Planner, 07/2007
LAB: Automation and Control Research Center, College of Automation, NJUPT
Advisor: Professor Jie Luo
Description:

The bus transit trip planner enabled users to input a bus route number to look up all bus stations the bus will stop at, or input a bus station name to search for all bus routes which would pass through the station, or input a starting point and a point of destination to list all possible routes to get to the destination. I built a database using SQL server and designed a database-based algorithm in MATLAB to calculate all possible bus routes. The user interface was built with Java. For more information, please refer to the research report.

bus trip planner

Example of searching for all possible routes to get to a destination

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