2009.9-2012.3 Shanghai Jiao Tong University (SJTU), Master of Engineering in Integrated Circuit Engineering
Rank: 10/55
2005.9-2009.7 Nanjing University of Posts and Telecommunications (NJUPT), Bachelor of Science in Automation
Rank: 3/104


Linear Algebra and Analytic Geometry (95/100) Advanced Mathematics (92/100)
Probability, Statistics and Stochastic Process (100/100) Physics (99/100)
Digital Signal Processing (96/100) Digital Circuits and Systems (96/100)
Signal and Linear System (86/100) Data Structure (98/100)


2015.6-Present SynTest Technologies, Inc. | Intern
Superior: Dr. Laung-Terng Wang, President & CEO
Gained Design-for-Test (DFT) related knowledge.
Learning DFT Architectures and Test Techniques

– Studying DFT architectures and test techniques, including Scan Design, Test Compression, Logic Built-In Self-Test (BIST), Boundary-Scan (IEEE Std 1149.1), and Core-Based Testing, particularly, those supported at SynTest.

Low-Pin-Count Scan Compression Software (UltraScan) Automation

– Automating UltraScan, SynTest low-pin-count scan compression synthesis tool, to further reduce test application time, including enhancing its existing Standard Test Interface Language (STIL) parser to fully comply with the IEEE Std 1450.6;

– UltraScan uses a time-division multiplexing/demultiplexing technique to shift scan patterns and test responses in and out of scan chains at a higher speed. This work is still on-going and expected to be completed around March 2016.

2012.3-2014.6 Cadence Design Systems, Inc., Shanghai | Product Engineer (PE)
Superior: Taufik Arifin, Group Director of Product Engineering

Enhanced my skills in analyzing Engineering Change Order (ECO) related backend problems; broadened my knowledge of backend design flow on Encounter Digital Implementation (EDI).

Customer Support
– Optimized and maintained ECO flow in EDI for better performance;

– Developed customized programs written in PERL or TCL language per customers’ technical requirements.

R&D Engineer Support
– Evaluated and analyzed the feasibility of EDI enhancement requirements from customers;

– Developed behavioral models for R&D engineers based on the feasibility analysis.

Product Validation Engineer Support

– Developed test patterns for functional validation of new EDI features.

2011.6-2012.3 Cadence Design Systems, Inc., Shanghai | Product Validation (PV) Intern
Superior: Hong Xu, Sr. PV Manager
Broadened my knowledge of timing optimization.
Regression Test & Analysis
– Analyzed all failure PV test cases to find and report EDI bugs;

– Migrated PV test cases into Multi-Mode Multi-Corner (MMMC) mode.

New Feature Testing
– Developed test programs and tested multi-CPU supporting performance of the engine for timing optimization.


2009.9-2012.3 System Level Chip Design Center, SJTU | Research Assistant
Advisors: Prof. Qin Wang and Dr. Jing Xie, School of Microelectronics
Low-Power Bus Encoding Scheme for AMBA Based System-on-Chip (SoC) Design

Developed a low-power bus encoding scheme which significantly reduced dynamic power introduced by crosstalk on AMBA AHB and AMBA AXI buses.

– Implemented a low-power bus encoding scheme in Verilog HDL;

– Synthesized and verified the design using Synopsys Design Compiler (DC) and VCS.

Peripheral Intellectual Property (IP) Core Design

Developed a Serial Peripheral Interface (SPI) and a General Purpose Input Output (GPIO) for an AMBA-based multi-core SoC design. (Government Property)

– Implemented SPI and GPIO in Verilog HDL;

– Verified the design using Synopsys VCS.

FFT-based Chirp Scaling Algorithm (CSA) Implementation

Implemented and optimized the FFT-based CSA for Synthetic Aperture Radar (SAR) data processing. Its purpose was to evaluate a 16-core DSP architecture adopted in an AMBA-based multi-core SoC design. (Government Property)

– Implemented the CSA in C language;

– Optimized the algorithm by serialization and parallelization for evaluating the parallel computing ability and the memory cost of the DSP architecture.

2007.7-2009.6 Automation and Control Research Center, NJUPT | Research Assistant

Advisor: Prof. Jie Luo, College of Automation

A Genetic Algorithm (GA) Based PID Parameters Optimization System

Developed a PID (proportion, integral, differential) optimizer to search for a set of PID parameters in obtaining an optimal step response, which had smaller overshoot and better rate of convergence compared to traditional methods, for a negative-feedback control system. (Report)

– Developed a PID optimizer using MATLAB GA Tool;
– Built a PID controller model in MATLAB SIMULINK;

– Developed a closed-loop system allowing real-time communication between the PID optimizer and the PID controller model.

A Bus Transit Trip Planner

The system enabled users to input a bus route number to look up all bus stations the bus will stop at, or input a bus station name to search for all bus routes which would pass through the station, or input a starting point and a point of destination to list all possible routes to get to the destination. (Report)

– Built a database using SQL server;
– Designed a database-based algorithm in MATLAB to calculate all possible bus routes;
– Built a user interface with Java.


2008, 2007 & 2006 Excellent Academic Scholarship, three times
2008 & 2007 National Scholarship (for top 1% undergraduate students), twice
2007 National College-Level Mathematical Modeling Contest Second-Class Prize
2007 University Fellowship (for top 5% undergraduate students)


[1] Xiaohong Li and Jing Xie, “A Hybrid Low-Power Bus Encoding Scheme for AMBA-Based SoC Design,” in Electrical Engineering, Electronics Engineering and Communications of the World Congress on Engineering and Technology (CET). 2011. (pdf)


2007.5-2007.8 Biology and math volunteer tutor for senior high school students
2005.9-2008.6 Committee member of Students Association
Participated and organized a lot of student activities, including annual inter-school debate contests, inter-school parties, celebrity lectures, etc.


Programming Languages
C/C++, Java, Verilog HDL, MATLAB, PERL, TCL
EDA Tools
  VCS (Synopsys), Design Compiler (Synopsys), Encounter (Cadence Design Systems)
English Proficiency
GRE: Verbal 139, Quantitative 165, Analytical Writing 3.0
TOEFL: 90; Reading 27, Listening 23, Speaking 20, Writing 20